Figure 7.20: The clocked RS flip-flop can be constructed from an RS flip-flop and two additional gates, the schematic symbol for the static clocked RSFF and its truth table.
We first consider the static clocked (level-sensitive) RS flip-flop shown in figure 7.20. The symbol x in the following tables represents either the binary state 0 or 1.
Figure 7.20: The clocked RS flip-flop can be constructed
from an RS flip-flop and two additional gates, the schematic symbol
for the static clocked RSFF and its truth table.
The first five lines in the truth table give the static input and output states. The last four lines show the state of the outputs after a complete clock pulse p.